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Receiver

For maximum linearity of response, the MWA will use a direct RF sampling receiver architecture. The receiver consists of all components between the RF output of the analog antenna tile beamformer, and a high spectral resolution (10 kHz) digital data stream transmitted to the central processing facility. In this case, the "F" part of the "FX" correlator architecture becomes part of the receiver, in conjunction with the fine polyphase filterbank at the correlator.

The receiver consists of two parts. The front end is a small analog & mixed-signal board consisting of fixed low-pass and sky-noise equalization filters, final amplifiers, and fast (Atmel) A/D converters sampling the RF in the 1st Nyquist zone. The back end is a purely digital part implementing coarse spectral filtering, decimation to a selected 30.72 MHz subset , and aggregation of signals for fibre transport to the central processing facility, where the fine spectral filtering to 3K channels of 10 kHz resolution takes place.

The Receiver System

The receiver system will accept the RF data stream from 8 antenna tiles on coaxial cable and will output digital data streams on optical fibre. It will digitize the input RF signal after appropriate signal conditioning and pass the digitized stream through a coarse polyphase filter to obtain 1.28 MHz wide "coarse" channels. 24 coarse channels, with a bandwidth of 30.72 MHz per antenna will be selected for transmission. Each receiver ‘node’ enclosure contains sufficient Monitor & Control and receiver related hardware to service 8 antenna tiles.

The 16 RF signals from eight analog beamformers enter the node enclosure through coaxial cables. They are fed to a Signal Conditioning Board to limit the bandwidth and adjust the power levels to suit the range of the digitizers. The Analog-to-Digital converters will be clocked at fs = 655.36 MHz. The digital data is fed to FPGA hardware in which a coarse polyphase filter bank is implemented to select the 24 sub-bands yielding a total of ~31 MHz bandwidth cove rage from the full antenna tile bandwidth of 80-300 MHz. The digitized data is aggregated and reformatted for transmission via 3 optic fibres to the correlator.

The node will contain additional components, including (a) Monitor & Control (m&c) capability to control the digital and analog hardware, relay and monitor beam-steering commands, and monitor environment and system health, (b) sampling clock module, and (c) possible driver electronics for synchronous phase-switching. The node enclosure will be weather tight, protected against lightning and RFI tight to avoid significant spurious emissions.

The principal components associated with the receiver node are shown in the schematic in Figure 1, and Figure 2 shows a schematic of the receiver monitor and control subsystem.

Figure 1. The principal components at the Receiver
Node.

Figure 1. The principal components at the Receiver Node.